Training in VLSI Design-Front End

EDA Partners & Tools

Mentor Graphics

         MODELSIM – HDL Simulation

Xilinx

         Xilinx ISE (Integrated Software Environment) – HDL Synthesis

Detailed Course Contents

Module - 1: Introduction to VLSI

       ✓ Scope of VLSI
       ✓ Today’s VLSI Design
       ✓ Introduction to CMOS Technology
       ✓ VLSI Design Flow
       ✓ ASIC Vs FPGA
       ✓ Design Methodologies
       ✓ Introduction to Verification Methodologies

Module - 2: Advanced Digital Design

 ✔ Introduction to Digital Electronics
 ✔ Universal Logic Elements
 ✔ Combinational Circuits - Design and Analysis
          ✓ Arithmetic Circuits
          ✓ Data processing Circuits
 ✔ Sequential Circuits - Design and Analysis
          ✓ Latches and Flip flops
          ✓ Shift Registers and Counters
          ✓ Memories – ROM and RAM
 ✔ Finite State Machine

Module– 3: Verilog HDL – RTL Coding and Synthesis

 ✔ Introduction to Verilog HDL
          ✓ Scope and Applications of Verilog HDL
          ✓ Verilog HDL language concepts
          ✓ Verilog language basics and constructs
          ✓ Abstraction levels
 ✔ Data Types
          ✓ Type concept
          ✓ Nets and registers
          ✓ Constants
          ✓ Arrays
 ✔ Verilog Operators
          ✓ Logical operators
          ✓ Bitwise and Reduction operators
          ✓ Concatenation and Conditional
          ✓ Relational and arithmetic
          ✓ Shift and Equality operators
          ✓ Operators precedence
 ✔ Styles of Modeling
          ✓ Structural Modeling
          ✓ Data Flow Modeling
              ✓ Continuous Assignments
          ✓ Behavioral Modeling
              ✓ Procedural Assignments
              ✓ Blocking and Non-Blocking assignments
              ✓ Conditional Statements

MODULE - 4: FPGA Implementation

MODULE – 5: Case Study – RTL Coding, Synthesis and FPGA Implementation


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